2008 -2010 Verification Engineer @ Caustic Graphics Inc.
2006 -2008 Asic and Fpga Verification Consultant @ Burton Lo Engineering
2006 -2008 Engineering Consultant @
1999 -2006 Engineer @
1994 -1999 Hardware Engineer @
Burton Lo Education
University of California, Berkeley
Bachelor of Science (Electrical Engineering, Computer Science)
1994
Burton Lo Skills
ASIC
Verilog
FPGA
Debugging
Simulations
SoC
Ethernet
Testing
Application-Specific Integrated Circuits (ASIC)
Field-Programmable Gate Arrays (FPGA)
VHDL
SystemVerilog
Analog
RTL Design
UVM
Functional Verification
Perl
Python (Programming Language)
Integrated Circuits (IC)
Computer Networking
Computer Graphics
telecom
Scripting
RTL Verification
RTL Coding
Burton Lo Summary
Burton Lo, based in San Francisco, CA, US, is currently a Principal Fpga Verification Engineer at Velodyne Lidar, Inc.. Burton Lo brings experience from previous roles at Facebook, Imagination Technologies, Caustic Graphics Inc. and Burton Lo Engineering. Burton Lo holds a Bachelor of Science in Electrical Engineering, Computer Science @ University of California, Berkeley. With a robust skill set that includes ASIC, Verilog, FPGA, Debugging, Simulations and more. Burton Lo has 1 emails and 1 mobile phone numbers on RocketReach.
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