Burton Lo Email & Phone Number
Principal Fpga Verification Engineer @ Velodyne Lidar
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Burton Lo Location
- San Francisco, CA, US
Burton Lo Work
- Principal Fpga Verification Engineer @ (February 2019 - Present)
- Verification Engineer @ (November 2017 - April 2018)
- Senior Hardware Engineer @ (December 2010 - September 2017)
- Verification Engineer @ Caustic Graphics Inc. (May 2008 - December 2010)
- Asic and Fpga Verification Consultant @ Burton Lo Engineering (February 2006 - April 2008)
- Engineering Consultant @ (January 2006 - January 2008)
- Engineer @ (September 1999 - February 2006)
- Hardware Engineer @ (June 1994 - September 1999)
Burton Lo Education
- University of California, Berkeley
Bachelor of Science (Electrical Engineering, Computer Science)
1994
Burton Lo Skills
- ASIC
- Verilog
- FPGA
- Debugging
- Simulations
- SoC
- Ethernet
- Testing
- Application-Specific Integrated Circuits (ASIC)
- Field-Programmable Gate Arrays (FPGA)
- VHDL
- SystemVerilog
- Analog
- RTL Design
- UVM
- Functional Verification
- Perl
- Python (Programming Language)
- Integrated Circuits (IC)
- Computer Networking
- Computer Graphics
- telecom
- Scripting
- RTL Verification
- RTL Coding
Burton Lo Summary
- Burton Lo, based in San Francisco, CA, US, is currently a Principal Fpga Verification Engineer at Velodyne Lidar, Inc.. Burton Lo brings experience from previous roles at Facebook, Imagination Technologies, Caustic Graphics Inc. and Burton Lo Engineering. Burton Lo holds a Bachelor of Science in Electrical Engineering, Computer Science @ University of California, Berkeley. With a robust skill set that includes ASIC, Verilog, FPGA, Debugging, Simulations and more. Burton Lo has 1 emails and 1 mobile phone numbers on RocketReach.
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