Brian Werst Email & Phone Number
Timing Convergence Lead for numerous variants of Xeon based memory controller (MC) IPs. @ Intel Corporation
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Brian Werst Location
- Fort Collins, CO, US
Brian Werst Work
- 2015 -now Timing Convergence Lead for numerous variants of Xeon based memory controller (MC) IPs. @
- 2013 -2015 PD Technical Lead plus the primary scalable fabric (PSF) owner @
- 2011 -2013 PD Technical Lead @
- 2009 -2011 FPU Technical Team Lead @
- 2005 -2009 Design Engineer - FPU Team @
- 1998 -2005 Design Engineer @
Brian Werst Education
- Wright State University
Master of Engineering - MEng (Electrical and Electronics Engineering)
1996-1998 - Wright State University
Bachelor of Engineering - BE (Electrical and Electronics Engineering)
1990-1996
Brian Werst Skills
- Catia
- PTC Creo
- GD&T
- Engineering
- ANSYS
Brian Werst Summary
- Brian Werst, based in Fort Collins, CO, US, is currently a Timing Convergence Lead for numerous variants of Xeon based memory controller (MC) IPs. at Intel. Brian Werst brings experience from previous roles at Intel Corporation. Brian Werst holds a 1996 - 1998 Master of Engineering - MEng in Electrical and Electronics Engineering @ Wright State University. With a robust skill set that includes Catia, PTC Creo, GD&T, Engineering, ANSYS and more. Brian Werst has 3 emails and 2 mobile phone numbers on RocketReach.
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