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Brian Wan Location
Singapore
Brian Wan Work
2025 -now SMTS Silicon Design Engineer @
2022 -2026 MTS Silicon Design Engineer @
2018 -2022 Senior Layout Engineer @
2014 -2018 Analog Layout Design Engineer @
2013 -2014 Contractor (Layout Engineer) @
2012 -2013 Layout Design Engineer, Senior @ Altera Corporation (M) Sdn Bhd
2010 -2012 Layout Design Engineer, Advanced @ Altera Corporation (M) Sdn Bhd
2008 -2010 Layout Design Engineer @ Altera Corporation (M) Sdn Bhd
Brian Wan Education
Universiti Putra Malaysia
Bachelor of Electrical & Electronic Engineering (MicroElectronics)
2004-2008
SMK Taman Desa (High School)
Sijil Tinggi Pelajaran Malaysia (STPM) (Pre-University)
2002-2003
Brian Wan Skills
Layout
EDA
ASIC
CMOS
DRC
FPGA
VLSI
LVS
Cadence Virtuoso
Physical Design
Calibre
Mask Design
Layout Tools
Unix Operating Systems
Hardware
IC
Floorplanning
Perl
Analog
Cadence
Brian Wan Summary
Brian Wan, based in Singapore, is currently a SMTS Silicon Design Engineer at AMD. Brian Wan brings experience from previous roles at AMD, Xilinx and Manpower Staffing. Brian Wan holds a 2004 - 2008 Bachelor of Electrical & Electronic Engineering in MicroElectronics @ Universiti Putra Malaysia. With a robust skill set that includes Layout, EDA, ASIC, CMOS, DRC and more. Brian Wan has 2 emails on RocketReach.
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