Brian Slater Email & Phone Number
Lead Verification Engineer @ Netronome
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Brian Slater Location
- Boston, MA, US
Brian Slater Work
- 2013 -now Lead Verification Engineer @
- 2011 -2013 Fpga Design Verification Manager @
- 2010 -2011 Principal Fpga Design Verification Engineer @
- 2006 -2008 Senior Consulting Engineer @
- 2005 -2006 Senior Consulting Engineer @
- 2005 -2005 Senior Consulting Engineer @
- 2003 -2005 Senior Asic Design Verification Engineer @
- 2002 -2002 Senior Asic Design Verification Engineer @ Cratos Networks
- 2001 -2002 Senior Asic Design Verification Engineer @
- 2000 -2001 Senior Fpga Design Verification Engineer @
- 1999 -2000 Asic Design Verification Engineer @ Quarry Technologies
- 1997 -1999 Fpga Design Verification Engineer @ Nortel Networks
- 1995 -1997 Asic Design Engineer and Co-Op Asic Design Verification Engineer @
Brian Slater Education
- Northeastern University
Master Of Science (Management, Engineering)
1998-2003 - Rensselaer Polytechnic Institute
Bachelor Of Science (Electrical Engineering)
1992-1997 - Archbishop Stepinac H.S 1988-1992
Brian Slater Skills
- Verilog
- Perl
- ASIC
- Debugging
- FPGA
- SystemVerilog
- VMM
- VERA
- RVM
- C++
- C
- SystemC
- Make
- VCS
- DVE
- 10G Ethernet LAN/WAN
- IPv4/IPv6
- XAUI
- MPLS
- SPI-4.2
- AMBA AHB
- PCIe
- USB 2.0
- ATM
- SONET
- NCSim
- System on a Chip (SoC)
Brian Slater Summary
- Brian Slater, based in Boston, MA, US, is currently a Lead Verification Engineer at Netronome. Brian Slater brings experience from previous roles at Motorola, Paradigm Works, Inc. and Cypress Semiconductor Corporation. Brian Slater holds a 1998 - 2003 Master Of Science in Management, Engineering @ Northeastern University. With a robust skill set that includes Verilog, Perl, ASIC, Debugging, FPGA and more. Brian Slater has 2 emails and 2 mobile phone numbers on RocketReach.
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