Bhaskar Vedula Email & Phone Number
IP Design Verification Engineer @ Intel Corporation
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Bhaskar Vedula Location
- United States
Bhaskar Vedula Work
- Technical Program Committee Member @ Dvcon China (January 2025 - Present)
- Technical Program Committe Member @ DVCon Europe (January 2025 - Present)
- Technical Program Committee Member @ DAC, The Chips to Systems Conference (December 2024 - Present)
- Senior IEEE Member @ (August 2024 - Present)
- Technical program committee member @ (June 2024 - Present)
- IP Design Verification Engineer @ (August 2019 - Present)
- Verification Engineer @ (August 2016 - July 2019)
- Graphics Hardware Engineer @ (October 2010 - August 2016)
- Internship @ (July 2009 - August 2010)
Bhaskar Vedula Education
- Manipal Institute of Technology
Master's degree (VLSI)
2008-2010 - Jawaharlal Nehru Technological University
Bachelor of Engineering - BE (Electronics and Instrumentation)
2004-2008
Bhaskar Vedula Skills
- ASIC
- Computer Architecture
- Debugging
- Event Management
- FPGA
- Functional Verification
- Logic Design
- Microprocessors
- ModelSim
- Open Verification Methodology
- Power Management
- Processors
- Python
- RTL design
- SoC
- Static Timing Analysis
- System on a Chip (SoC)
- SystemVerilog
- Team Leadership
- Technical Leadership
- Universal Verification Methodology (UVM)
- VHDL
- VLSI
- Verification and Validation (V&V)
- Verilog
- Very-Large-Scale Integration (VLSI)
- ovm
- review
Bhaskar Vedula Summary
- Bhaskar Vedula, based in United States, is currently a IP Design Verification Engineer at Intel Corporation. Bhaskar Vedula brings experience from previous roles at Dvcon China, DVCon Europe, DAC, The Chips to Systems Conference and IEEE. Bhaskar Vedula holds a 2008 - 2010 Master's degree in VLSI @ Manipal Institute of Technology. With a robust skill set that includes ASIC, Computer Architecture, Debugging, Event Management, FPGA and more. Bhaskar Vedula has 4 emails and 1 mobile phone numbers on RocketReach.
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