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Bart McDaniel Location
Phoenix, AZ, US
Bart McDaniel Work
Principal Layout Engineer (RFIC and Analog) @ (March 2019 - Present)
Principal Layout Design Engineer (RFIC and Analog) @ (March 2019 - March 2019)
Layout Design Engineer (contract) @ (September 2013 - April 2015)
Layout Design Engineer (contract) @ (September 2012 - September 2013)
Sr Staff Analog Design Engineer @ INTEL CORP (January 1987 - January 2011)
Bart McDaniel Education
Arizona State University
course work for Doctor of Philosophy (Ph.D.) -(18 hours) (EE)
The University of Kansas
Bachelor of Science and Master of Science (Electrical Engineering)
Bart McDaniel Skills
CMOS
Analog Circuit Design
Mixed Signal
IC
Analog
PLL
Semiconductors
Integrated Circuit Design
LNA
Circuit Design
Device Drivers
Embedded Systems
ASIC
VLSI
Physical Verification
Signal Integrity
SRAM
SoC
Cadence
EDA
Testing
RF
Microprocessors
Cadence Virtuoso
Processors
Physical Design
Low-power Design
Simulations
RF Engineering
Floorplanning
DAC
Power Management
SERDES
Debugging
DRC
Agilent ADS
LVS
Spectre
Spectrum Analyzer
Semiconductor Process Technology
Electrical Engineering
Verilog
Intel
BiCMOS
SPICE
Hardware Architecture
DFT
PCB design
ADCs
Silicon
Power
Layout Design
Design
Lpi
Low Power Design
Bart McDaniel Summary
Bart McDaniel, based in Phoenix, AZ, US, is currently a Principal Layout Engineer (RFIC and Analog) at Intrinsix Corp.. Bart McDaniel brings experience from previous roles at Intrinsix Corp., Freescale Semiconductor, Qualcomm and INTEL CORP. Bart McDaniel holds a course work for Doctor of Philosophy (Ph.D.) -(18 hours) in EE @ Arizona State University. With a robust skill set that includes CMOS, Analog Circuit Design, Mixed Signal, IC, Analog and more. Bart McDaniel has 3 emails and 1 mobile phone numbers on RocketReach.
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