Avinay Pandey Email
VLSI layout Intern @ Tevatron Technologies Pvt. Ltd.
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Avinay Pandey Location
- Noida, UP, IN
Avinay Pandey Work
- VLSI layout Intern @ (February 2014 - Present)
- Vocational Summer Trainee @ (May 2012 - June 2012)
Avinay Pandey Education
- Suresh Gyan Vihar University, jaipur
Master of Technology (M.Tech.) (VLSI)
2012-2014 - Suresh Gyan Vihar University, Jaipur
Bachelor of Technology (B.Tech.) (Electronics and Communication Engineering)
2009-2013 - St. Joseph School, Shaktinagar
(Mathematics and Science)
1994-2008
Avinay Pandey Summary
- Avinay Pandey, based in Noida, UP, IN, is currently a VLSI layout Intern at Tevatron Technologies Pvt. Ltd.. Avinay Pandey brings experience from previous roles at NTPC. Avinay Pandey holds a 2012 - 2014 Master of Technology (M.Tech.) in VLSI @ Suresh Gyan Vihar University, jaipur.
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