Avinash Tripathi Email

Avinash Tripathi Skills

• ASIC
• Analog
• Analog Circuit Design
• Analog Design
• Application-Specific Integrated Circuits (ASIC)
• CMOS
• Cadence Virtuoso
• EDA
• Expertise in circuit design of PLL(charge pump, PFD, Filter, Oscillators, Level Shifters, current reference), PMC blocks(POR, Power Fail detector and Regulators) and Bias Generator blocks. Involvement in BE SoC integration reviews of SAR-ADC in 16ffc projects. Involved in doing layout of different Analog subblocks and PLL top.  Streamlining the deliveries of 3rd Party landing IP(PLL) at different delivery milestones.  Managing a layout team of 6 people working on different Analog IPs across 5nm,16ffc and C40 technologies.  Leading Global Methodology team to ensure traceability of Electrical specs of different Analog IPs and driving the Quality control of design/layout for those IPs.  Leading Global View Generation team to provide and track Front End and Back End views(Timing, DFT, gds, netlist, Redhawk, LEF, behavioral model) on time with quality delivery.  Worked closely with the SoC integration team, Validation team and Test team across different projects.  Holding 4 US Patents and 1 Defensive Publication.  Had been a part of “Analog Hiring Team” to hire and mentor fresh/experienced employees.  Worked on LSF compute closely with IT team rationing and prioritizing the critical/trivial batch jobs availability for Analog team members working on different projects.
• IC
• Integrated Circuit Design
• Low-power Design
• Mixed Signal
• PLL
• Semiconductors
• SoC
• System on a Chip (SoC)
• VLSI
• Verilog
• Very-Large-Scale Integration (VLSI)