Aswin Venkatesh Email & Phone Number
ASIC Engineer @ Cisco
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Aswin Venkatesh Location
- San Jose, CA, US
Aswin Venkatesh Work
- ASIC Engineer @ (May 2024 - Present)
- Digital Design Engineer - Staff @ (April 2023 - May 2024)
- Digital Design Engineer - Sr @ (October 2021 - March 2023)
- FPGA Design Engineer @ (January 2019 - September 2021)
- Graduate Research Assistant @ (November 2017 - November 2018)
- Hardware Engineering Intern @ (May 2018 - August 2018)
- Research Assistant @ Solarillion Foundation (June 2016 - July 2017)
- Undergraduate Research Assistant @ Solarillion Foundation (August 2015 - May 2016)
- Student Trainee @ (December 2014 - December 2014)
Aswin Venkatesh Education
- Stony Brook University
Master's degree (Electrical and Computer Engineering)
2017-2018 - Anna University, Chennai
Bachelor’s Degree (Electrical and Electronics Engineering)
2012-2016
Aswin Venkatesh Skills
- Verilog
- System Verilog
- System on a Chip (SoC)
- RTL Development
- RISC-V
- ARM M0+
- ML Accelerators
- Microprocessor Design
- Digital Design (FPGA & ASIC)
- Static Timing Analysis
- Python (Programming Language)
- Field-Programmable Gate Arrays (FPGA)
- Embedded Systems
- Firmware Development
- Matlab
- C
- HTML
- C++
- RTL Design
- Cadence Virtuoso
Aswin Venkatesh Summary
- Aswin Venkatesh, based in San Jose, CA, US, is currently a ASIC Engineer at Cisco. Aswin Venkatesh brings experience from previous roles at TDK InvenSense and Stony Brook University. Aswin Venkatesh holds a 2017 - 2018 Master's degree in Electrical and Computer Engineering @ Stony Brook University. With a robust skill set that includes Verilog, System Verilog, System on a Chip (SoC), RTL Development, RISC-V and more. Aswin Venkatesh has 2 emails and 1 mobile phone numbers on RocketReach.
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Aswin Venkatesh
ASIC Engineer
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