Ashwin Pai Email & Phone Number
CAD Engineer DFT @ Apple
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Ashwin Pai Location
- Austin, TX, US
Ashwin Pai Work
- CAD Engineer DFT @ (July 2021 - Present)
- IP Design Engineer @ (June 2016 - July 2021)
- Design for Test Intern @ (September 2015 - December 2015)
- Student Assistant @ (January 2015 - August 2015)
- DFT Consultant (via SmartPlay Technologies) @ (December 2012 - June 2014)
- Project Engineer @ (July 2011 - July 2012)
Ashwin Pai Education
- University of Florida
Master of Science (M.S.)
- Mahatma Gandhi University, Keralam
Bachelor of Technology (BTech)
Ashwin Pai Skills
- ATPG Scan coverage analysis
- CAD Methodology
- Clock and Reset Domain Crossing
- DFT
- DFT Scan synthesis, compression and insertion
- Flow Regressions
- Front-End RTL SignOff
- Jenkins
- Mentor Tessent
- RTL Design
- RTL Linting
- RTL Static SignOff
- RTL synthesis
- Snyposys Design Compiler
- SystemVerilog
- TCL, PERL and Make
- NI LabVIEW
- Scan Insertion
- Development
- ATPG
- Test Engineering
- Mentor Graphics Embedded Test
- Cadence Virtuoso
- Synopsys Tetramax
- LTSpice
- Perl
- Intel
- IP
- Competitive Analysis
- Verilog
- C And C++
- Mbist
- Agilent ADS
- Makefile
- Cadence Spectre
- Design
- Digital Synthesis
- Unix
- Embedded Test
- Sta Fundamentals
- Lbist
- Verification
- Analysis
Ashwin Pai Summary
- Ashwin Pai, based in Austin, TX, US, is currently a CAD Engineer DFT at Apple. Ashwin Pai brings experience from previous roles at Intel Corporation, Broadcom Corporation, Dept of Housing and Residence Education and Broadcom Research India Pvt Ltd. Ashwin Pai holds a Master of Science (M.S.) @ University of Florida. With a robust skill set that includes ATPG Scan coverage analysis, CAD Methodology, Clock and Reset Domain Crossing, DFT, DFT Scan synthesis, compression and insertion and more. Ashwin Pai has 2 emails and 3 mobile phone numbers on RocketReach.
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