Ashutosh Garg Email & Phone Number
Principal Member of Technical Staff @ AMD
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Ashutosh Garg Location
- Folsom, CA, US
Ashutosh Garg Work
- Principal Member of Technical Staff @ (June 2024 - Present)
- Senior Member Of Technical Staff @ (June 2020 - June 2024)
- Microarchitect @ (January 2017 - June 2020)
- Technical Lead @ (January 2013 - December 2017)
- Senior Hardware Design Engineer @ (September 2008 - January 2013)
- Graduate Technical Intern @ (June 2008 - September 2008)
- Teaching Assistant @ (April 2008 - July 2008)
Ashutosh Garg Education
- California State University-Sacramento
Master of Business Administration (MBA) (Finance, General)
2010-2012 - Stanford University
MS (Electrical Engineering)
2007-2008 - California State University, Fresno
B.S. (Electrical Engineer)
2004-2007
Ashutosh Garg Skills
- 3D Graphics
- ASIC
- Application-Specific Integrated Circuits (ASIC)
- C
- C++
- Circuit Design
- Computer Architecture
- Computer Graphics
- Debugging
- EDA
- Embedded Systems
- FPGA
- Floating Point Arithmatic
- Functional Verification
- Hardware Architecture
- Integrated Circuit Design
- Logic Design
- Machine Learning
- Matlab
- Microprocessors
- ModelSim
- Perl
- RTL Design
- Semiconductors
- Simulations
- SoC
- SystemVerilog
- VHDL
- VLSI
- Verilog
- Very-Large-Scale Integration (VLSI)
- Intel
- Application Specific Integrated Circuits Asic
- Design
- Very Large Scale Integration Vlsi
- Application Specific Integrated Circuits
- Very Large Scale Integration
Ashutosh Garg Summary
- Ashutosh Garg, based in Folsom, CA, US, is currently a Principal Member of Technical Staff at AMD. Ashutosh Garg brings experience from previous roles at AMD and Intel Corporation. Ashutosh Garg holds a 2010 - 2012 Master of Business Administration (MBA) in Finance, General @ California State University-Sacramento. With a robust skill set that includes 3D Graphics, ASIC, Application-Specific Integrated Circuits (ASIC), C, C++ and more. Ashutosh Garg has 3 emails and 1 mobile phone numbers on RocketReach.
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