Ashok Jaiswal Email & Phone Number
Principal Manager @ Socionext Inc.
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Ashok Jaiswal Location
- Munich, BY, DE
Ashok Jaiswal Work
- Principal Manager @ (April 2026 - Present)
- Senior Manager @ (July 2022 - March 2026)
- Senior Manager Mixed Signal Design @ (October 2020 - July 2022)
- Design Project Manager @ (November 2014 - September 2020)
- Research Engineer @ Technical University of Darmstadt (July 2009 - October 2014)
- Concept Engineer @ Qimonda (June 2006 - March 2009)
- Design Engineer @ (June 2004 - May 2006)
Ashok Jaiswal Education
- Technische Universität Darmstadt
Doctor of Philosophy (Ph.D.) (Integrated Electronic Systems)
2009-2014 - Indian Institute of Technology, Delhi
M.Tech (Integrated Electronics & Circuits)
2002-2004 - Kamla Nehru Institute of technology
B.Tech (Electronics)
1998-2002
Ashok Jaiswal Skills
- Verilog
- ASIC
- Functional Verification
- Low-power Design
- SystemVerilog
- CMOS
- VHDL
- Analog
- Semiconductors
- Mixed Signal
- IC
- VLSI
- Circuit Design
- Cadence Virtuoso
- ModelSim
- Simulations
- SoC
- Physical Design
- Integrated Circuit Design
- Static Timing Analysis
- RTL design
- Microprocessors
- TCL
- Silicon
- EDA
- FPGA
- Signal Processing
- Analog Circuit Design
- Microelectronics
- Digital Signal Processors
- Xilinx
- Matlab
- Microcontrollers
- Digital Circuit Design
- Algorithms
- Cadence
- Hardware Architecture
- Electronics
- ARM
- SystemC
- System on a Chip Soc
- Verification
- Very Large Scale Integration Vlsi
- Power
- Integrated Circuits Ic
- Application Specific Integrated Circuits Asic
- Field Programmable Gate Arrays Fpga
- Engineering
- Illustrator
- Design
- Low Power Design
- SQL
- Power Management
- Intel
Ashok Jaiswal Summary
- Ashok Jaiswal, based in Munich, BY, DE, is currently a Principal Manager at Socionext Europe. Ashok Jaiswal brings experience from previous roles at Socionext Europe, Infineon Technologies and Technical University of Darmstadt. Ashok Jaiswal holds a 2009 - 2014 Doctor of Philosophy (Ph.D.) in Integrated Electronic Systems @ Technische Universität Darmstadt. With a robust skill set that includes Verilog, ASIC, Functional Verification, Low-power Design, SystemVerilog and more. Ashok Jaiswal has 5 emails and 1 mobile phone numbers on RocketReach.
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