Ashika Kumar Email & Phone Number
Physical Design Engineer Lead @ Intel Corporation
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Ashika Kumar Location
- California, United States
Ashika Kumar Work
- 2022 -now Physical Design Engineer Lead @
- 2018 -2021 SD Engineering Manager @
- 2017 -2018 Senior Application Engineer II @
- 2011 -2017 Senior Component Design Engineer @
- 2010 -2011 Sr. Design Engineer @
- 2007 -2010 Applications Engineer @
- 2006 -2007 Research Assistant @
- 2005 -2006 Project Assistant @ IISc
Ashika Kumar Education
- Visvesvaraya Technological University
Ashika Kumar Skills
- EDA
- Static Timing Analysis
- Physical Design
- Timing Closure
- ASIC
- Low-power Design
- TCL
- Verilog
- VLSI
- SoC
- RTL design
- SystemVerilog
- Formal Verification
- DRC
- Primetime
- Clock Tree Synthesis
- Integrated Circuit Design
- Physical Verification
- Logic Synthesis
- Functional Verification
- ModelSim
- DFT
- Cadence Virtuoso
- RTL coding
- CMOS
- LVS
- Logic Design
- Signal Integrity
- IC
- Floorplanning
- Timing
- Very-Large-Scale Integration (VLSI)
- System on a Chip (SoC)
- Integrated Circuit
- Design
- Low Power Design
- Very Large Scale Integration Vlsi
- Component Design
- Very Large Scale Integration
Ashika Kumar Summary
- Ashika Kumar, based in California, United States, is currently a Physical Design Engineer Lead at Intel Corporation. Ashika Kumar brings experience from previous roles at Intel Corporation, Synopsys Inc and Renesas Mobile Corporation. Ashika Kumar holds a Visvesvaraya Technological University. With a robust skill set that includes EDA, Static Timing Analysis, Physical Design, Timing Closure, ASIC and more. Ashika Kumar has 4 emails on RocketReach.
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