Aseem Jain Email
ASIC Architect – Subsystem Architecture and ASIC Power @ Meta
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Aseem Jain Location
- Austin, TX, US
Aseem Jain Work
- 2022 -now ASIC Architect – Subsystem Architecture and ASIC Power @
- 2018 -2022 SoC Power Modeling and Optimization Lead @
- 2014 -2018 CPU Implementation, PPA, Clock and Power Lead @
- 2011 -2014 Sr. Staff IC Design @
- 2005 -2011 Sr. Design Engineer @
- 2003 -2005 Design Engineer @
Aseem Jain Education
- Kurukshetra University
(Communication, Electronics)
1998-2002
Aseem Jain Skills
- Physical Design
- Timing Closure
- SoC
- ASIC
- Static Timing Analysis
- RTL design
- IC
- Power Management
- Primetime
- Low-power Design
- Clock Tree Synthesis
- Physical Verification
- Floorplanning
- EDA
- Functional Verification
- Application-Specific Integrated Circuits (ASIC)
- Verilog
- System on a Chip (SoC)
- Very-Large-Scale Integration (VLSI)
- VLSI
- Application Specific Integrated Circuits Asic
- Low Power Design
- Very Large Scale Integration Vlsi
- System On A Chip Soc
- Application Specific Integrated Circuits
- Very Large Scale Integration
- System on a Chip
Aseem Jain Summary
- Aseem Jain, based in Austin, TX, US, is currently a ASIC Architect – Subsystem Architecture and ASIC Power at Meta. Aseem Jain brings experience from previous roles at Apple, Qualcomm, Broadcom and Texas Instruments. Aseem Jain holds a 1998 - 2002 Kurukshetra University. With a robust skill set that includes Physical Design, Timing Closure, SoC, ASIC, Static Timing Analysis and more. Aseem Jain has 3 emails on RocketReach.
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