Arvind Vidyarthi Email & Phone Number
Sr. Director, SOC and IP Physical Design Implementation, Methodology and Automation @ Altera
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Arvind Vidyarthi Location
- Santa Clara, CA, US
Arvind Vidyarthi Work
- Sr. Director, SOC and IP Physical Design Implementation, Methodology and Automation @ (December 2023 - Present)
- Director, Global Physical Design Lead @ (April 2016 - Present)
- Ucsc Silicon Valley Vlsi Engineering Advisory Group @ (May 2021 - Present)
- Faculty and Instructor for Vlsi and Physical Design @ (June 2011 - March 2017)
- Senior Pd Manager @ (November 2012 - April 2016)
- Senior Manager, Physical Design @ (May 2007 - October 2012)
- Senior Cad Engineer @ (June 2006 - May 2007)
- Hardware Engineer, MTS @ (September 2004 - June 2006)
- Cad Engineering Intern @ (May 2004 - September 2004)
- Summer Intern @ (May 2001 - August 2001)
Arvind Vidyarthi Education
- Tufts University
Master of Science (Electrical Engineering)
2002-2004 - Binghamton University
Master of Science (Electrical Engineering)
2000-2002 - Harcourt Butler Technological Institute (HBTI)
Bachelor of Technology (Electronics Engineering)
1996-2000 - Lamartiniere College 1985-1995
Arvind Vidyarthi Skills
- Physical Design
- Timing Closure
- Static Timing Analysis
- P&R
- Floorplanning
- Clock Tree Synthesis
- Primetime
- Perl
- TCL
- CVS
- Control Theory
- Digital Signal Processors
- SoC
- IC
- VLSI
- EDA
- ASIC
- Processors
- Microprocessors
- Mixed Signal
- Analog
- Application-Specific Integrated Circuits (ASIC)
- Circuit Design
- EDA/IP Negotiations
- ML/AI Initiatives
- SOC Physical Design & Tapeout
- SOC Timing Closure
- SPICE
- System on a Chip (SoC)
- Tools Flows and Methodologies
- Very-Large-Scale Integration (VLSI)
- Design
- Analytical Skill
- Engineering
- Interconnects
- Semiconductors
- Analysis
- System on a Chip Soc
- Application Specific Integrated Circuits Asic
- Very Large Scale Integration Vlsi
- Very Large Scale Integration
- System on a Chip
- Application Specific Integrated Circuits
Arvind Vidyarthi Summary
- Arvind Vidyarthi, based in Santa Clara, CA, US, is currently a Sr. Director, SOC and IP Physical Design Implementation, Methodology and Automation at Altera. Arvind Vidyarthi brings experience from previous roles at Intel Corporation, Ucsc Extension Silicon Valley and Nvidia. Arvind Vidyarthi holds a 2002 - 2004 Master of Science in Electrical Engineering @ Tufts University. With a robust skill set that includes Physical Design, Timing Closure, Static Timing Analysis, P&R, Floorplanning and more. Arvind Vidyarthi has 4 emails and 2 mobile phone numbers on RocketReach.
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