Arvind Raghavan Email & Phone Number
Senior RTL Designer @ ASIC North
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Arvind Raghavan Location
- Milpitas, CA, US
Arvind Raghavan Work
- Senior RTL Designer @ (August 2024 - Present)
- Principal Engineer @ (September 2019 - February 2024)
- Senior Program Manager @ (February 2011 - September 2019)
- Principal Engineer @ (March 2010 - March 2011)
- Member of Technical Staff, ASIC @ (June 2006 - March 2010)
- Senior MTS - Design @ (January 2004 - June 2006)
- Member of Technical Staff @ (April 2000 - December 2003)
Arvind Raghavan Education
- Indian Institute of Technology, Madras
B.Tech (Electronics and Communication Engineering)
- Indian Institute of Technology, Madras
MS (Electrical Engineering)
- University of Maryland
MS (Electrical Engineering)
- UCLA Anderson School of Management
MBA (FE)
Arvind Raghavan Skills
- Program Management
- Optical Communications
- Application-Specific Integrated Circuits (ASIC)
- ASIC
- Verilog
- FPGA
- SystemVerilog
- Semiconductors
- Simulations
- Synopsys tools
- EDA
- SoC
- Ethernet
- Primetime
- RTL design
- Mixed Signal
- CMOS
- Field-Programmable Gate Arrays (FPGA)
- Public Relations
- Team Leadership
- Optical Transport Network (OTN)
- Synchronous Digital Hierarchy (SDH)
- Project Management
- OTN
- SDH
- SATA
- Fibre Channel
- Optical Network
- Member of Toastmasters
- Toastmasters
- Analytical Skills
- CDC
- Communication
- Communication Protocols
- Computer Arithmetic
- Design Specifications
- Digital Designs
- LEC
- Leadership
- Linting
- Logic Synthesis
- Low-power Design
- Microarchitecture
- Microsoft Office
- Negotiation
- Oral Communication
- Organization Skills
- Persuasion
- Power Analysis
- Presentations
- Problem Solving
- Product Development
- Project Plans
- RDC
- RTL Development
- Silicon Validation
- Static Timing Analysis
- Technical Discussions
- Timelines
- Timing Closure
- Vendor Management
- Work Breakdown Structure (WBS)
- Written Communication
- NCSim
- Cadence
- VHDL
- SONET
- SQL
- Telecommunications
- Application Specific Integrated Circuits Asic
- Synchronous Digital Hierarchy Sdh
- Linux
- Management
- Field Programmable Gate Arrays Fpga
- SAN
- Graphic Design
- Testing
- Optical Transport Network Otn
- Program Manager
- Application Specific Integrated Circuits
- Field Programmable Gate Arrays
- Optical Transport Network
- Synchronous Digital Hierarchy
Arvind Raghavan Summary
- Arvind Raghavan, based in Milpitas, CA, US, is currently a Senior RTL Designer at ASIC North. Arvind Raghavan brings experience from previous roles at Infinera. Arvind Raghavan holds a B.Tech in Electronics and Communication Engineering @ Indian Institute of Technology, Madras. With a robust skill set that includes Program Management, Optical Communications, Application-Specific Integrated Circuits (ASIC), ASIC, Verilog and more. Arvind Raghavan has 2 emails and 1 mobile phone numbers on RocketReach.
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