Arthas Xiao's Location

San Jose, CA, US

Arthas Xiao's Work

  • Staff ASIC Design @ Pixelworks
  • FPGA Design and Verification Engineer @ Tellabs
  • FPGA Verification Engineer @ Huawei

Arthas Xiao's Education

  • Fudan University

    Master's degree (Electrical and Electronics Engineering)

    2007 - 2010
  • Huazhong University of Science and Technology

    Bachelor's degree (Telecommunications Engineering)

    2001 - 2005

Arthas Xiao's Skills

  • UVM
  • Ethernet
  • Digital IC Design
  • RTL design
  • Verification
  • Perl Script
  • SDH
  • Video
  • ASIC
  • Verilog

Arthas Xiao's Summary

Arthas Xiao, based in San Jose, CA, US, is currently a Staff ASIC Engineer at Pixelworks, bringing experience from previous roles at Pixelworks, Sigma Designs and Tellabs Access & Data Dept. Arthas Xiao holds a 2007 - 2010 Master's degree in Electrical and Electronics Engineering @ Fudan University. With a robust skill set that includes UVM, Ethernet, Digital IC Design, RTL design, Verification and more, Arthas Xiao contributes valuable insights to the industry. Arthas Xiao has 1 email on RocketReach.

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