Archana Vyas Email
Principal Product Validation Engineer, FED @ Cadence Design Systems
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Archana Vyas Location
- Faridabad, HR, IN
Archana Vyas Work
- Principal Product Validation Engineer, FED @ (July 2017 - Present)
- Member of Technical Staff @ (July 2014 - Present)
- Software Engineer @ (May 2013 - June 2014)
- Intern @ (June 2012 - May 2013)
- Trainee @ (June 2011 - December 2011)
Archana Vyas Education
- Y.M.C.A UST
Bachelor of Technology (B.Tech.) (Electrical, Electronics and Communications Engineering)
2008-2012 - AGGARWAL PUBLIC SCHOOL
12th and 10th
1998-2008
Archana Vyas Skills
- Microsoft Office
- Teamwork
- Microsoft Word
- Design
- Programming
- PowerPoint
- Electronics
- Microsoft Excel
- Product Validation
- English
- Java
- Testing
- Social Media
- JavaScript
- C
- Windows
Archana Vyas Summary
- Archana Vyas, based in Faridabad, HR, IN, is currently a Principal Product Validation Engineer, FED at Cadence Design Systems. Archana Vyas brings experience from previous roles at Cadence Design Systems and STMicroelectronics. Archana Vyas holds a 2008 - 2012 Bachelor of Technology (B.Tech.) in Electrical, Electronics and Communications Engineering @ Y.M.C.A UST. With a robust skill set that includes Microsoft Office, Teamwork, Microsoft Word, Design, Programming and more. Archana Vyas has 2 emails on RocketReach.
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