Aravinth J Email
Senior Silicon Design Engineer @ AMD
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Aravinth J Location
- Virudhunagar, TN, IN
Aravinth J Work
- Senior Silicon Design Engineer @ (October 2025 - Present)
- Staff Design Engineer @ (April 2025 - October 2025)
- Senior Design Engineer @ (April 2021 - March 2025)
- Design Engineer @ (July 2017 - November 2020)
- DFT Trainee @ Sykatia Technologies (June 2016 - June 2017)
Aravinth J Education
- Bannari Amman Institute of technology
Master of Engineering (M.Eng.) (VLSI DESIGN)
2014-2016 - SSM COLLEGE OF ENGINEERING
Bachelor of Engineering (BE) (Electronics and Communications Engineering)
2009-2013 - Devangar Higher secondary school
+2 (Computer Science)
2008-2009
Aravinth J Skills
- VLSI
- C
- Perl
- Verilog
- Scan,Fault Models,LOC,LOS
- Joint Test Action Group (JTAG)
- BIST
Aravinth J Summary
- Aravinth J, based in Virudhunagar, TN, IN, is currently a Senior Silicon Design Engineer at AMD. Aravinth J brings experience from previous roles at Insemi Technology Services Pvt. Ltd., Tessolve and Sykatia Technologies. Aravinth J holds a 2014 - 2016 Master of Engineering (M.Eng.) in VLSI DESIGN @ Bannari Amman Institute of technology. With a robust skill set that includes VLSI, C, Perl, Verilog, Scan,Fault Models,LOC,LOS and more. Aravinth J has 3 emails on RocketReach.
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