Anurag Goyal Email & Phone Number
Sr. Design Engineer @ Google
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Anurag Goyal Location
- San Jose, CA, US
Anurag Goyal Work
- Sr. Design Engineer @ (October 2022 - Present)
- Sr. Design Engineer @ (May 2018 - October 2022)
- Hardware Engineer @ Signal Laboratories, Inc. (May 2017 - May 2018)
- Hardware Engineering Intern @ Signal Laboratories, Inc. (June 2016 - May 2017)
- Assistant Manager @ (June 2014 - June 2015)
- Research Intern @ (June 2013 - August 2013)
- Research Intern @ Solid State Physics Laboratory, Defense Research & Development Organisation (June 2012 - July 2012)
Anurag Goyal Education
- University of Southern California
Master’s Degree (Electrical and Electronics Engineering)
2015-2017 - National Institute of Technology Kurukshetra
Bachelor of Technology (B.Tech.) (Electrical, Electronics and Communications Engineering)
2010-2014
Anurag Goyal Skills
- Application-Specific Integrated Circuits (ASIC)
- C
- C++
- CMOS
- Cadence Encounter
- Cadence Virtuoso
- Computer Hardware
- DFT
- DRC
- Digital Circuit Design
- Engineering
- Field-Programmable Gate Arrays (FPGA)
- HSPICE
- LTE
- Matlab
- P&R
- Perl
- R
- RTL Design
- Signal Integrity
- Static Timing Analysis
- Synopsys Primetime
- System Verilog
- System on a Chip (SoC)
- SystemC
- SystemVerilog
- Testing
- VHDL
- Verilog
- Very-Large-Scale Integration (VLSI)
- Proteus
- Lattice
- Vehicles
- FTTx
- Code
- RF
- Field Programmable Gate Arrays Fpga
- Amplifiers
- Networking
- Consideration
- Oscillators
- Government
- Analog
- Prime
- CAD
- Nose
- SIM
- NCSim
- Xilinx
- COMSOL
- Microchip
- Collision
- Microsoft Office
- Programming
- Microsoft Word
- Microsoft Excel
- Acoustic
- Analytical Skill
- RTL coding
- FPGA
- Training
- PIC
- ModelSim
- Collision Detection
- MPLAB
- SQL
- IDE
- Cadence Spectre
- Surface
- Design
- Firmware
- IRIS
- Pspice
- Science
- Pwm
- Very Large Scale Integration Vlsi
- Orcad
- Transistors
- Surveillance
- Floor Planning
- Eagle
- DBMS
- Very Large Scale Integration
- Field Programmable Gate Arrays
Anurag Goyal Summary
- Anurag Goyal, based in San Jose, CA, US, is currently a Sr. Design Engineer at Google. Anurag Goyal brings experience from previous roles at AMD, Signal Laboratories, Inc. and Reliance Jio Infocomm Ltd.. Anurag Goyal holds a 2015 - 2017 Master’s Degree in Electrical and Electronics Engineering @ University of Southern California. With a robust skill set that includes Application-Specific Integrated Circuits (ASIC), C, C++, CMOS, Cadence Encounter and more. Anurag Goyal has 5 emails and 4 mobile phone numbers on RocketReach.
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