Anup Patil's Location
Santa Clara, CA, US
Anup Patil's Work
- Senior Staff Analog Design Engineer @ Marvell India
- Senior Analog Design Engineer @ Intel Corporation
- Analog Design Engineer @ Medtronic
- Front Office Assistant @ Arizona State University
- Student @ Arizona State University
- Database Administrator @ Cognizant
Anup Patil's Education
- Arizona State University
Master of Science - MS (Electrical engineering)
2013 - 2015 - Visvesvaraya Technological University
Bachelor of Engineering (B.E.) (Electronics and Communication Engineering)
2008 - 2012
Anup Patil's Skills
- C
- VHDL
- Verilog
- Perl
- C++
- Programming
- Primetime
- Encounter
- Cadence
- Cadence Virtuoso
Anup Patil's Summary
Anup Patil, based in Santa Clara, CA, US, is currently a Senior Staff Analog Design Engineer at Marvell Technology, bringing experience from previous roles at Intel Corporation, Medtronic and Arizona State University. Anup Patil holds a 2013 - 2015 Master of Science - MS in Electrical engineering @ Arizona State University. With a robust skill set that includes C, VHDL, Verilog, Perl, C++ and more, Anup Patil contributes valuable insights to the industry. Anup Patil has 3 emails and 1 mobile phone number on RocketReach.
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