Anuj Aggarwal's Location
Santa Clara, CA, US
Anuj Aggarwal's Work
- Working on Graphics and Visualization technologies @ AMD
- Senior Staff Engineer @ Marvell India
- Senior Manager @ Synopsys Inc
- Hardware Verification Engineer @ Oracle
- Staff Corporate Applications Engineer @ Synopsys Inc
- Lead Applications Engineer @ Cadence Design Systems
- Consulting Engineer @ Interra Information Technologies (InterraIT)
- Principal Software Engineer @ TEMIC (Usha Matra/Temic Usha)
- Design Engineer @ ER&DC
Anuj Aggarwal's Education
- PEC University of Technology
(Computer Science, Engineering)
1988 - 1992
Anuj Aggarwal's Skills
- EDA
- IC
- ASIC
- Functional Verification
- SystemVerilog
- VLSI
- Semiconductors
- Debugging
- FPGA
- Verilog
Anuj Aggarwal's Summary
Anuj Aggarwal, based in Santa Clara, CA, US, is currently a Working on Graphics and Visualization technologies at AMD, bringing experience from previous roles at Marvell Semiconductor, Synopsys Inc, Oracle and Synopsys. Anuj Aggarwal holds a 1988 - 1992 PEC University of Technology. With a robust skill set that includes EDA, IC, ASIC, Functional Verification, SystemVerilog and more, Anuj Aggarwal contributes valuable insights to the industry. Anuj Aggarwal has 2 emails on RocketReach.
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