Ankita Saxena's Location
New Delhi, DL, IN
Ankita Saxena's Work
- Staff Design Verification Engineer @ Marvell Technology
- System Design Engineer Intern - Hardware @ Marvell India
- Graduate Teaching Assistant @ California State University-Sacramento
Ankita Saxena's Education
- California State University-Sacramento
Master’s Degree (Electrical and Electronics Engineering)
2016 - 2018 - Guru Gobind Singh Indraprastha University
Bachelor’s Degree (Electrical and Electronics Engineering)
2012 - 2016 - Delhi Public School - Dwarka
High School
2006 - 2012
Ankita Saxena's Skills
- Verilog
- Timing Analysis
- Memory Hierarchy
- Cache Coherence
- Digital Circuit Design
- Integrated Circuit Design
- Semiconductors
- Cadence
- Xilinx
- Application Specific Integrated Circuits
Ankita Saxena's Summary
Ankita Saxena, based in New Delhi, DL, IN, is currently a Staff Design Verification Engineer at Marvell Technology, bringing experience from previous roles at Marvell Semiconductor and California State University-Sacramento. Ankita Saxena holds a 2016 - 2018 Master’s Degree in Electrical and Electronics Engineering @ California State University-Sacramento. With a robust skill set that includes Verilog, Timing Analysis, Memory Hierarchy, Cache Coherence, Digital Circuit Design and more, Ankita Saxena contributes valuable insights to the industry. Ankita Saxena has 1 email on RocketReach.
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