Aneri Jain Email
Silicon DFT Engineer @ Google
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Aneri Jain Location
- Bengaluru, KA, IN
Aneri Jain Work
- Silicon DFT Engineer @ (July 2022 - Present)
- Hardware Engineering Intern @ (January 2022 - July 2022)
- Undergraduate Research Fellow @ (August 2021 - January 2022)
- Electronics Product Design Intern @ (May 2021 - July 2021)
- ILDP Representative @ (June 2021 - June 2021)
- Micron Global Women's Mentorship Program @ (March 2021 - May 2021)
- Teaching Assistant @ (January 2021 - May 2021)
- Teaching Assistant @ (August 2020 - December 2020)
- Research Assistant @ Indian Institute of Information Technology, Allahabad (May 2020 - July 2020)
- Joint Coordinator @ Poetry club, BITS Pilani-Pilani Campus (July 2018 - August 2019)
- Research Intern @ (May 2019 - July 2019)
Aneri Jain Education
- Birla Institute of Technology and Science, Pilani
MS.c. ; B.E. (Mathematics; Electrical and Electronics)
2017-2022
Aneri Jain Skills
- C (Programming Language)
- C++
- Computer Architecture
- Digital Designs
- Digital Signal Processing
- LTspice
- Linux
- Matlab
- Microelectronics
- Python (Programming Language)
- Simulink
- Spyglass
- TCL
- VLSI
- Verilog
- calibre
- electronic devices
- tessent
Aneri Jain Summary
- Aneri Jain, based in Bengaluru, KA, IN, is currently a Silicon DFT Engineer at Google. Aneri Jain brings experience from previous roles at Google, cfaed - Center for Advancing Electronics Dresden, Luminous Power Technologies (P) Ltd and Hiroshima University. Aneri Jain holds a 2017 - 2022 MS.c. ; B.E. in Mathematics; Electrical and Electronics @ Birla Institute of Technology and Science, Pilani. With a robust skill set that includes C (Programming Language), C++, Computer Architecture, Digital Designs, Digital Signal Processing and more. Aneri Jain has 3 emails on RocketReach.
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