Aneesh P's Location
Bengaluru, KA, IN
Aneesh P's Work
- ASIC Digital Design Engineer @ NXP Semiconductors
- Senior Lead Engineer @ Qualcomm
- Senior Digital Designer @ Analog Devices
- Technical Lead @ NXP Semiconductors
- Senior Digital Designer @ NeST Technologies
Aneesh P's Education
- Mahatma Gandhi University
BTech - Bachelor of Technology (Electronics and Communications Engineering)
2007 - 2011
Aneesh P's Skills
- FPGA
- ASIC
- SoC
- Video Processing
- Digital Electronics
- DDR3
- Xilinx Vivado
- Debugging
- Functional Verification
- RTL design
Aneesh P's Summary
Aneesh P, based in Bengaluru, KA, IN, is currently a ASIC Digital Design Engineer at NXP Semiconductors, bringing experience from previous roles at Qualcomm, Analog Devices, NXP Semiconductors and NeST Technologies. Aneesh P holds a 2007 - 2011 BTech - Bachelor of Technology in Electronics and Communications Engineering @ Mahatma Gandhi University. With a robust skill set that includes FPGA, ASIC, SoC, Video Processing, Digital Electronics and more, Aneesh P contributes valuable insights to the industry. Aneesh P has 1 email on RocketReach.
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