Aneesh Mathew Email & Phone Number
Sr engineer Physical Design @ Texas Instruments
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Aneesh Mathew Location
- Allen, TX, US
Aneesh Mathew Work
- 2006 -now Sr engineer Physical Design @
- 2000 -2006 Project Leader VLSI and System Desgin @
Aneesh Mathew Education
- BIT Mesra Student-Industry Relations Cell
MS (Micro electronics)
2003-2005 - Karnatak University
BE (Electronics & Communication)
1994-1998 - St. Aloysius college mangalore
Aneesh Mathew Skills
- Static Timing Analysis
- ASIC
- VLSI
- TCL
- Physical Design
- SoC
- Timing Closure
- Clock Tree Synthesis
- Floorplanning
- EDA
- Primetime
- Physical Verification
- RTL design
- LVS
- DFT
- Formal Verification
- DRC
- Integrated Circuit Design
- CMOS
- Low-power Design
- IC
- Verilog
- Low Power Design
Aneesh Mathew Summary
- Aneesh Mathew, based in Allen, TX, US, is currently a Sr engineer Physical Design at Texas Instruments. Aneesh Mathew brings experience from previous roles at Wipro Technologies. Aneesh Mathew holds a 2003 - 2005 MS in Micro electronics @ BIT Mesra Student-Industry Relations Cell. With a robust skill set that includes Static Timing Analysis, ASIC, VLSI, TCL, Physical Design and more. Aneesh Mathew has 3 emails and 1 mobile phone numbers on RocketReach.
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