Analee Pacina Santiago's Location
Singapore
Analee Pacina Santiago's Work
- External Test Engineer @ Zarlink Semiconductor is now Microsemi
- Test Engineer @ Zarlink Semiconductor is now Microsemi
- Senior Test Engineer @ Advanced Interconnect Technologies
Analee Pacina Santiago's Education
- Cebu Institute of Technology
B.S. (Electrical Engineering)
1987 - 1992 - Holy Infant Academy
(Secondary)
1983 - 1987
Analee Pacina Santiago's Skills
- Semiconductors
- IC
- Semiconductor Industry
- Product Engineering
- Test Engineering
Analee Pacina Santiago's Summary
Analee Pacina Santiago, based in Singapore, is currently a External Test Engineer at Zarlink Semiconductor, bringing experience from previous roles at Zarlink and Advanced Interconnect Technologies. Analee Pacina Santiago holds a 1987 - 1992 B.S. in Electrical Engineering @ Cebu Institute of Technology. With a robust skill set that includes Semiconductors, IC, Semiconductor Industry, Product Engineering, Test Engineering and more, Analee Pacina Santiago contributes valuable insights to the industry. Analee Pacina Santiago has 1 email on RocketReach.
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