Amith Pai Email & Phone Number
Design Verification Engineer @ Apple
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Amith Pai Location
- Santa Clara, CA, US
Amith Pai Work
- 2021 -now Design Verification Engineer @
- 2019 -2021 Senior ASIC Verification Engineer @
- 2017 -2019 ASIC Verification Engineer @
- 2016 -2016 CPU Design Verification Intern @
- 2016 -2016 IP Verification Intern @
- 2014 -2015 Software Engineer @
- 2013 -2014 Associate Engineer @
- 2013 -2013 Research Assistant @
Amith Pai Education
- Texas A&M University
Master of Science (M.S.) (Computer Engineering)
2015-2017 - Birla Institute of Technology and Science, Pilani
Bachelor of Engineering (B.E.) (Electrical and Electronics Engineering)
2009-2013
Amith Pai Skills
- Cadence Virtuoso
- Digital Electronics
- Field Programmable Gate Arrays Fpga
- Cadence Virtuoso Layout
- Algorithms
- Analog Circuit Design
- C
- Perl
- Functional Verification
- Matlab
- Electronics
- Digital Design
- Image Processing
- Verilog
- Microcontrollers
- Xilinx
- Signal Processing
- Programming
- Microsoft Office
- Java
- Embedded Systems
- Labview
- FPGA
- VHDL
- C++
- ModelSim
- Universal Verification Methodology Uvm
- Physical Design
- Design
- Pspice
- Cadence Virtuoso Layout Editor
- Digital Image Processing
- Digital Circuit Design
- Verification
- Field Programmable Gate Arrays
- Universal Verification Methodology
Amith Pai Summary
- Amith Pai, based in Santa Clara, CA, US, is currently a Design Verification Engineer at Apple. Amith Pai brings experience from previous roles at NVIDIA and Qualcomm. Amith Pai holds a 2015 - 2017 Master of Science (M.S.) in Computer Engineering @ Texas A&M University. With a robust skill set that includes Cadence Virtuoso, Digital Electronics, Field Programmable Gate Arrays Fpga, Cadence Virtuoso Layout, Algorithms and more. Amith Pai has 3 emails and 2 mobile phone numbers on RocketReach.
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