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Amit Govil Location
San Jose, CA, US
Amit Govil Work
Principal Engineer @ (June 2024 - Present)
SOC Timing and Clocking Lead @ (May 2022 - June 2024)
SOC Lead and Senior Engineering Manager @ (February 2022 - May 2022)
SOC Lead @ (November 2018 - February 2022)
Staff Design Engineer @ (February 2015 - November 2018)
Senior Design Engineer @ (October 2011 - February 2015)
Senior Design Engineer @ Interra Systems (ARM client) (January 2010 - October 2011)
Physical design engineer @ (June 2008 - January 2010)
Amit Govil Education
Manipal Academy of Higher Education
Master of Science - MS (Microelectronics)
2009-2011
UCLA
PG Diploma in VLSI design (Microelectronics)
2008-2008
Visvesvaraya Technological University
BE (Electronics & Communications)
2004-2008
Amit Govil Skills
Analog Circuit Design
SRAM
IC
Characterization
Cadence Virtuoso
Circuit Design
VLSI
Low-power Design
Verilog
Perl
SoC
RF
Simulations
RTL design
Functional Verification
CMOS
Semiconductors
Design
Low Power Design
Very Large Scale Integration Vlsi
Very Large Scale Integration
Amit Govil Summary
Amit Govil, based in San Jose, CA, US, is currently a Principal Engineer at Arm. Amit Govil brings experience from previous roles at Intel Corporation and Arm. Amit Govil holds a 2009 - 2011 Master of Science - MS in Microelectronics @ Manipal Academy of Higher Education. With a robust skill set that includes Analog Circuit Design, SRAM, IC, Characterization, Cadence Virtuoso and more. Amit Govil has 2 emails on RocketReach.
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