Amaresh S Email
Design Verification Engineer @ Apple
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Amaresh S Location
- San Francisco, CA, US
Amaresh S Work
- Design Verification Engineer @ (July 2019 - Present)
- EOL Student Assistant @ (January 2018 - May 2019)
- Systems Engineer @ (February 2015 - June 2017)
Amaresh S Education
- North Carolina State University
Master's degree (Computer Engineering)
2017-2019 - Anna University Chennai
Undergraduate (Electrical and Electronics Engineering)
2010-2014
Amaresh S Skills
- Advanced Microarchitecture
- Algorithms
- Application-Specific Integrated Circuits (ASIC)
- Assertion Based Verification
- C (Programming Language)
- C++
- CUDA
- Compilers
- Computer architecture
- Data Structures
- Debugging
- Design Vision
- Functional Verification
- GPGPU-Sim
- GPU compute Architecture
- Hardware Description Language
- LLVM
- Linux
- Matlab
- Microsoft Excel
- Microsoft Office
- Microsoft Visual Studio C++
- ModelSim
- Object-Oriented Programming (OOP)
- Object-oriented Languages
- Parallel Computing
- Perl
- Programming
- Python
- Software Development
- Synopsys tools
- System on a Chip (SoC)
- SystemVerilog
- Universal Verification Methodology (UVM)
- Verilog
- random constrained testing
- tcl and shell scripting
- transaction level modelling
Amaresh S Summary
- Amaresh S, based in San Francisco, CA, US, is currently a Design Verification Engineer at Apple. Amaresh S brings experience from previous roles at North Carolina State University and Tata Consultancy Services. Amaresh S holds a 2017 - 2019 Master's degree in Computer Engineering @ North Carolina State University. With a robust skill set that includes Advanced Microarchitecture, Algorithms, Application-Specific Integrated Circuits (ASIC), Assertion Based Verification, C (Programming Language) and more. Amaresh S has 2 emails on RocketReach.
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Amaresh S
Design Verification Engineer
San Francisco, CA, US
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