Amaresh P. Email
Engineer @ Apple
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Amaresh P. Location
- Austin, TX, US
Amaresh P. Work
- Engineer @ (August 2021 - Present)
- Technical Lead @ Samsung Austin R & D (July 2019 - July 2021)
- Principal Engineer and Skill Group Lead @ (January 2009 - June 2019)
- IC Design Engineer @ (July 2003 - December 2008)
- Engineer @ (July 1995 - June 2003)
Amaresh P. Education
- Arizona State University
MS
1993-1995 - University of Mysore
Bachelor of Science (BS)
Amaresh P. Skills
- CMOS
- Clock Tree Synthesis
- Computer Architecture
- DRC
- Digital Circuit Design
- Digital IC Design
- EDA
- FPGA
- Floorplanning
- Formal Verification
- IC
- Integrated Circuit Design
- LVS
- Logic Design
- Logic Synthesis
- Low-power Design
- Microarchitecture
- Parasitic Extraction
- Place
- Primetime
- RTL coding
- Semiconductors
- Signal Integrity
- SoC
- TCL
- Timing
- Timing Closure
Amaresh P. Summary
- Amaresh P., based in Austin, TX, US, is currently a Engineer at Apple. Amaresh P. brings experience from previous roles at Samsung Austin R & D, ARM, AMD and Intel. Amaresh P. holds a 1993 - 1995 MS @ Arizona State University. With a robust skill set that includes CMOS, Clock Tree Synthesis, Computer Architecture, DRC, Digital Circuit Design and more. Amaresh P. has 1 emails on RocketReach.
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