Akshay Patel Email & Phone Number
Principal Dv Engineer @ Quantenna Communications
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Akshay Patel Location
- Santa Clara, CA, US
Akshay Patel Work
- Principal Dv Engineer @ (July 2015 - Present)
- Senior Staff Asic Verification Engineer @ (January 2012 - July 2015)
- Principal Asic Verif Engineer @ (May 2010 - January 2012)
- Senior Member Technical Staff @ (March 2008 - April 2010)
- Verification Manager @ (March 2006 - March 2008)
- Senior Asic Verification Engineer @ (September 2005 - March 2006)
- Asic Verification Engineer @ E-Infochips (October 1997 - September 2005)
- Research and Development Engineer @ (January 1992 - September 1997)
Akshay Patel Education
- Dharamsinh Desai University
(Communication, Electronics)
1986-1991
Akshay Patel Skills
- C (Programming Language)
- Python (Programming Language)
- Universal Verification Methodology (UVM)
- SoC
- Verilog
- SystemVerilog
- ASIC
- IC
- VLSI
- RTL design
- Perl
- Debugging
- Processors
- Simulations
- Functional Verification
- Testing
- FPGA
- System on a Chip (SoC)
Akshay Patel Summary
- Akshay Patel, based in Santa Clara, CA, US, is currently a Principal Dv Engineer at Quantenna Communications. Akshay Patel brings experience from previous roles at Huawei Technologies, Ericsson, Sibridge Technologies and Appliedmicro. Akshay Patel holds a 1986 - 1991 Dharamsinh Desai University. With a robust skill set that includes C (Programming Language), Python (Programming Language), Universal Verification Methodology (UVM), SoC, Verilog and more. Akshay Patel has 2 emails and 4 mobile phone numbers on RocketReach.
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