Akhil Garg's Location
Noida, Uttar Pradesh, India
Akhil Garg's Work
- SoC DFT Head @ STMicroelectronics
- SoC DFT Design Manager @ NXP Semiconductors
- Senior Principal Design Engineer @ NXP Semiconductors
- Staff Application Engineer @ Synopsys Inc
- Principal Product Engineer @ Cadence Design Systems
- Senior Member of Techincal Staff @ Cadence Design Systems
- Technical Leader (DFT) @ STMicroelectronics
- Senior Design Engineer @ STMicroelectronics
Akhil Garg's Education
- Indian Institute of Technology, Delhi
MS(R) (Integrated Electronic Circuits)
2009 - 2012 - Dr. A.P.J. Abdul Kalam Technical University
Bachelors in Technology (Electronics and Communication)
2000 - 2004 - Delhi Public School, Vidyut Nagar
Intermediate (Science)
1989 - 2000
Akhil Garg's Skills
- Design for Test
- Digital Design
- Synthesis
- Static Timing Analysis
- ATPG
- RTL design
- Verilog
- SoC
- Formal Verification
- VLSI
Akhil Garg's Summary
Akhil Garg, based in Noida, Uttar Pradesh, India, is currently a SoC DFT Head at STMicroelectronics, bringing experience from previous roles at NXP Semiconductors, Synopsys Inc and Cadence Design Systems. Akhil Garg holds a 2009 - 2012 MS(R) in Integrated Electronic Circuits @ Indian Institute of Technology, Delhi. With a robust skill set that includes Design for Test, Digital Design, Synthesis, Static Timing Analysis, ATPG and more, Akhil Garg contributes valuable insights to the industry. Akhil Garg has 2 emails on RocketReach.
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