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Ajay Singh Location
Milpitas, CA, US
Ajay Singh Work
2020 -now Soc Verification @
2019 -2020 Design Verification @
2016 -2019 Verification Architect and Design verification lead @
2012 -2016 Design verification lead @
2008 -2012 Principal Verification Engineer, Design IP @
2007 -2008 Staff Design engineer @
2005 -2007 Staff Design Engineer @
2005 -2005 Sr Verification Engineer @ Contract at Cisco
2002 -2005 Sr Design engineer @
1998 -1998 MTS @ VLSi software
Ajay Singh Education
National Institute of Technology Kurukshetra
MTech (Electrical Enginering)
1995-1997
Amravati University
BE (Electronics and Communications Engineering)
1991-1995
Ajay Singh Skills
SystemVerilog
Functional Verification
Verilog
ASIC
Specman
Debugging
UVM
Open Verification Methodology
FPGA
Semiconductors
RTL design
SoC
ModelSim
IC
NCSim
Logic Synthesis
Simulations
EDA
VLSI
Formal Verification
Processors
Microprocessors
Perl
Cadence
Logic Design
Mixed Signal
Wireless Networking
Questa
Team Management
IMC
Vmanager
Simvision
Hiring
C
Xilinx
Hardware
Synopsys tools
Computer Architecture
Scripting
Integrated Circuit Design
Graphic Design
Field Programmable Gate Arrays Fpga
System on a Chip Soc
Sales
Strategic Planning
Very Large Scale Integration Vlsi
Integrated Circuits Ic
Universal Verification Methodology Uvm
Application Specific Integrated Circuits Asic
Ajay Singh Summary
Ajay Singh, based in Milpitas, CA, US, is currently a Soc Verification at Socionext US. Ajay Singh brings experience from previous roles at Quanergy, Samsung Semiconductor, Inc., Xilinx and Cadence Design Systems. Ajay Singh holds a 1995 - 1997 MTech in Electrical Enginering @ National Institute of Technology Kurukshetra. With a robust skill set that includes SystemVerilog, Functional Verification, Verilog, ASIC, Specman and more. Ajay Singh has 3 emails and 4 mobile phone numbers on RocketReach.
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