Aditya Pawar Email & Phone Number
Sr Silicon Design Engineer @ AMD
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Aditya Pawar Location
- Boxborough, MA, US
Aditya Pawar Work
- Sr Silicon Design Engineer @ (February 2020 - Present)
- CPU Design Verification Engineer @ (February 2019 - December 2019)
- Design Verification Intern @ (November 2018 - February 2019)
- Signal Integrity Intern @ (January 2018 - November 2018)
- IC Design Intern @ (August 2017 - November 2017)
- Graduate Teaching Assistant @ (January 2017 - March 2017)
Aditya Pawar Education
- Portland State University
Master’s Degree (Electrical and Computer Engineering)
2016-2017 - K. J. Somaiya Institute of Technology
Bachelor of Engineering (B.E.) (Electronics and Telecommunications)
2010-2014
Aditya Pawar Skills
- Security
- Digital Electronics
- Microsoft Office
- Verilog
- VHDL
- Matlab
- Microsoft Excel
- Microsoft Word
- PowerPoint
- C++
- Microchip PIC
- ARM
- Wireshark
- SystemVerilog
- Application Specific Integrated Circuits
- Static Timing Analysis
- Field Programmable Gate Arrays
- Python
- Embedded C
- Computer Architecture
- Synopsys tools
- ModelSim
- Cadence Virtuoso
- Embedded Systems
- Simulations
- Very Large Scale Integration
Aditya Pawar Summary
- Aditya Pawar, based in Boxborough, MA, US, is currently a Sr Silicon Design Engineer at AMD. Aditya Pawar brings experience from previous roles at Wave Computing, Cisco and Analog Rails. Aditya Pawar holds a 2016 - 2017 Master’s Degree in Electrical and Computer Engineering @ Portland State University. With a robust skill set that includes Security, Digital Electronics, Microsoft Office, Verilog, VHDL and more. Aditya Pawar has 2 emails and 5 mobile phone numbers on RocketReach.
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