Aditya Barve Email & Phone Number
Senior Silicon Design Verification Engineer @ Google
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Aditya Barve Location
- Mountain View, CA, US
Aditya Barve Work
- 2022 -now Senior Silicon Design Verification Engineer @
- 2019 -2022 Silicon Engineer @
- 2019 -2019 Staff Design Verification Engineer @
- 2017 -2019 Senior Design Verification Engineer @
- 2014 -2017 Senior Hardware Engineer @
- 2013 -2014 Graphics Power Intern @
- 2011 -2011 Summer Intern @
Aditya Barve Education
- Georgia Institute of Technology 2012-2014
- Sri Jayachamarajendra College of Engineering 2008-2012
- Sadvidya Composite Pre University College 2006-2008
Aditya Barve Skills
- Verilog
- VHDL
- VLSI
- Java
- Computer Architecture
- Spectre
- Matlab
- Microcontrollers
- Logic Design
- Cadence Virtuoso
- C++
- Logic Synthesis
- NI LabVIEW
- COMSOL
- Digital Image Processing
- Atmel AVR
- Multisim
- Xilinx
- Embedded C
- DSP
- 8051 Assembly
- ModelSim
- Agilent
- Microprocessors
- x86 Assembly
- Keil
- Digital Electronics
- Cadence Spectre
- Encounter
- Synopsys Design Vision
- Synopsys tools
- C
- mbed
- VLSI CAD
- Perl
- P6 architecture
- netburst architecture
- SPICE
- presto
- Nanohub
- FETtoy
- Mathematics
- Returns
- Screening
- AVR
- Windows
- Functional Verification
- Scattering
- Analog
- Programming
- Particle
- Autonomous
- Labview
- Scholarships
- Acid
- Physical Design
- Design
- Cosim
- Robotics
- Professional Courses
- Science
- Sri
- Incisive
- Signal
- Guidance
- RTL design
- Copies
- Serdes Architecture
- Bangalore
- Engineering
- TCL
- Integrated Circuits Ic
- Meter
- Testing
- Lab Bringup
- Learner
- Solution
- IEEE
- Solution Based
- Fed
- Hardware
- Verdi
- Shell Scripting
- Probe
- Apb
- System On A Chip Soc
- New Delhi
- Control Logic
- System Verilog
- Atmega
- Icc
- Communication
- Turbo C
- Circuit Design
- National Level
- Workshops
- Stage
- Light Scattering
- Interactive Advertising
- Indian
- Intensity
- Data Driven Testing
- Project
- Fourth
- Static Timing Analysis
- Fuzzy Logic
- Very Large Scale Integration Vlsi
- I2C
- Nature
- Subversion
- Laser
- Virtual Instrumentation
- Electronics
- Control Systems Design
- Software
- CMOS
- Questa
- Application Specific Integrated Circuits Asic
- India
- Cash
- Theory
- Mdio
- Universal Verification Methodology Uvm
- Synopsys Primetime
- Light
- Semiconductors
- Beam
- Marks
- Application Specific Integrated Circuits
- Universal Verification Methodology
- System on a Chip
- Integrated Circuits
- Very Large Scale Integration
Aditya Barve Summary
- Aditya Barve, based in Mountain View, CA, US, is currently a Senior Silicon Design Verification Engineer at Google. Aditya Barve brings experience from previous roles at Google, Inphi Corporation and Oracle. Aditya Barve holds a 2012 - 2014 Georgia Institute of Technology. With a robust skill set that includes Verilog, VHDL, VLSI, Java, Computer Architecture and more. Aditya Barve has 5 emails and 4 mobile phone numbers on RocketReach.
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