Adithya Ramesh Location
- San Jose, CA, US
Adithya Ramesh Work
- 2025 -now RISC-V Soft CPU Design Engineer @
- 2025 -2025 Digital Design Engineer @
- 2024 -2025 IC Design Intern @
- 2023 -2024 Teaching Assistant @
- 2021 -2022 Automation Test Engineer @
- 2021 -2021 Quality Engineering and Assurance Intern @
Adithya Ramesh Education
- Worcester Polytechnic Institute
Master of Science - MS (Electrical and Computer Engineering)
2022-2024 - Shanmugha Arts, Science, Technology and Research Academy
Bachelor of Technology - BTech (Electronics and Communication Engineering)
2017-2021
Adithya Ramesh Summary
- Adithya Ramesh, based in San Jose, CA, US, is currently a RISC-V Soft CPU Design Engineer at Altera. Adithya Ramesh brings experience from previous roles at Western Semiconductor, Worcester Polytechnic Institute and Cognizant. Adithya Ramesh holds a 2022 - 2024 Master of Science - MS in Electrical and Computer Engineering @ Worcester Polytechnic Institute. Adithya Ramesh has 1 emails on RocketReach.
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