Adithya Ramesh Email
RISC-V Soft CPU Design Engineer @ Altera
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Adithya Ramesh Location
- San Jose, CA, US
Adithya Ramesh Work
- RISC-V Soft CPU Design Engineer @ (March 2025 - Present)
- Digital Design Engineer @ (January 2025 - March 2025)
- IC Design Intern @ (August 2024 - January 2025)
- Teaching Assistant @ (September 2023 - May 2024)
- Automation Test Engineer @ (August 2021 - July 2022)
- Quality Engineering and Assurance Intern @ (March 2021 - July 2021)
Adithya Ramesh Education
- Worcester Polytechnic Institute
Master of Science - MS (Electrical and Computer Engineering)
2022-2024 - Shanmugha Arts, Science, Technology and Research Academy
Bachelor of Technology - BTech (Electronics and Communication Engineering)
2017-2021
Adithya Ramesh Summary
- Adithya Ramesh, based in San Jose, CA, US, is currently a RISC-V Soft CPU Design Engineer at Altera. Adithya Ramesh brings experience from previous roles at Western Semiconductor, Worcester Polytechnic Institute and Cognizant. Adithya Ramesh holds a 2022 - 2024 Master of Science - MS in Electrical and Computer Engineering @ Worcester Polytechnic Institute. Adithya Ramesh has 1 emails on RocketReach.
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