Senior Design Verification Engineer @ (October 2023 - February 2025)
Senior Design Verification Engineer @ (March 2020 - September 2023)
SOC Design Verification Engineer @ (July 2018 - February 2020)
Student Assistant - FPGA and Embedded Programmer @ FREEDM System Center (June 2017 - December 2017)
Web Solutions Specialist @ (November 2015 - April 2016)
Adarsh Singh Education
North Carolina State University
Master of Science (MS) (Computer Engineering)
2016-2018
MCT's Rajiv Gandhi Institute Of Technology
Bachelor of Engineering (BE) (Electronics and Telecommunication)
2011-2015
KC college, Mumbai
Higher Secondary (Science)
2009-2011
Adarsh Singh Skills
Altera Quartus
C
C++
CUDA
Computer Architecture
Data Structures
Embedded Systems
Java
Linux
Modelsim
NI LabVIEW
Object-Oriented Programming (OOP)
OpenCL
Programing
Programming
RTL Design
Verilog
Vulkan
Adarsh Singh Summary
Adarsh Singh, based in San Jose, CA, US, is currently a Senior Design Verification Engineer at Meta. Adarsh Singh brings experience from previous roles at Apple and FREEDM System Center. Adarsh Singh holds a 2016 - 2018 Master of Science (MS) in Computer Engineering @ North Carolina State University. With a robust skill set that includes Altera Quartus, C, C++, CUDA, Computer Architecture and more. Adarsh Singh has 2 emails and 2 mobile phone numbers on RocketReach.
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