Aashutosh Garg Email
Senior Silicon Design Engineer @ AMD
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Aashutosh Garg Location
- Delhi, India
Aashutosh Garg Work
- Senior Silicon Design Engineer @ (July 2024 - Present)
- Senior Product Specialist @ (April 2024 - June 2024)
- Product Specialist II @ (April 2022 - March 2024)
- Product Specialist @ (July 2020 - March 2022)
Aashutosh Garg Education
- Netaji Subhas Institute of Technology
Bachelor of Engineering - BE (Electrical, Electronics and Communications Engineering)
2016-2020
Aashutosh Garg Skills
- Application-Specific Integrated Circuits (ASIC)
- Clock Tree Synthesis
- Debugging
- Digital IC Design
- Glitch
- Low-power Design
- Power Analysis
- Power Estimation
- Power Optimization
- Power Reduction
- PowerArtist
- Problem Solving
- Python (Programming Language)
- RTL power
- Scripting
- Scriptwriting
- Static Timing Analysis
- Static and dynamic power
- SystemVerilog
- TCL
- Technical Support
- Unified Power Format (UPF)
- Verilog
Aashutosh Garg Summary
- Aashutosh Garg, based in Delhi, India, is currently a Senior Silicon Design Engineer at AMD. Aashutosh Garg brings experience from previous roles at Ansys. Aashutosh Garg holds a 2016 - 2020 Bachelor of Engineering - BE in Electrical, Electronics and Communications Engineering @ Netaji Subhas Institute of Technology. With a robust skill set that includes Application-Specific Integrated Circuits (ASIC), Clock Tree Synthesis, Debugging, Digital IC Design, Glitch and more. Aashutosh Garg has 1 emails on RocketReach.
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