Veeramani V's Location
Bengaluru, KA, IN
Veeramani V's Work
- Senior SoC Architect @ NVIDIA
- Senior ASIC Design Engineer @ NVIDIA
- Associate @ Genpact Headstrong Capital Markets
- Intern @ EPFL (École polytechnique fédérale de Lausanne)
Veeramani V's Education
- Indian Institute of Technology, Kanpur
B.Tech (Electrical Engineering)
2002 - 2006 - SSV
High School (Mathematics and Computer Science)
1992 - 2002
Veeramani V's Skills
- RTL design
- Microarchitecture
- RTL verification
- ASIC
- Verilog
- SoC
- Static Timing Analysis
- Functional Verification
- Logic Synthesis
- Computer Architecture
Veeramani V's Summary
Veeramani V, based in Bengaluru, KA, IN, is currently a Assistant Vice President at Jio, bringing experience from previous roles at Jio and NVIDIA. Veeramani V holds a 2002 - 2006 B.Tech in Electrical Engineering @ Indian Institute of Technology, Kanpur. With a robust skill set that includes RTL design, Microarchitecture, RTL verification, ASIC, Verilog and more, Veeramani V contributes valuable insights to the industry. Veeramani V has 2 emails and 1 mobile phone number on RocketReach.
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