Jack Zhu's Location
San Jose, CA, US
Jack Zhu's Work
- DDR Controller Architect, Principal R and D Engineer @ Synopsys Inc
- Engineering Director and Principal Architect @ Marvell India
- Principal Architect @ Marvell India
- Executive Engineering Project Lead @ Vweb Corporation
- Director of ASIC Design @ Vweb Corporation
- ASIC Design Manager @ ESS Technology, Inc.
- Design Manager @ Divio Inc. (Acquired by ESS in 2003)
Jack Zhu's Education
- Peking University
MSCS
- Peking University
BSCS
Jack Zhu's Skills
- SoC
- IC
- Verilog
- Application-Specific Integrated Circuits (ASIC)
- Semiconductors
- Embedded Systems
- Debugging
- Field-Programmable Gate Arrays (FPGA)
- RTL Design
- EDA
Jack Zhu's Summary
Jack Zhu, based in San Jose, CA, US, is currently a DDR Controller Architect, Principal R and D Engineer at Synopsys Inc, bringing experience from previous roles at Marvell Semiconductor, Marvell and Vweb Corporation. Jack Zhu holds a MSCS @ Peking University. With a robust skill set that includes SoC, IC, Verilog, Application-Specific Integrated Circuits (ASIC), Semiconductors and more, Jack Zhu contributes valuable insights to the industry. Jack Zhu has 2 emails on RocketReach.
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