Location
San Jose, California, United States
Work
- ASIC Design Engineer @ Google
- SoC RTL Design Engineer @ Intel Corporation
- Senior RTL Design Engineer @ Oracle
- Hardware Engineer II @ Oracle
- HW Engineer Intern @ Intel Corporation
- HW Engineer Intern @ Intel Corporation
Education
- University of Southern California
MS (Electrical - VLSI + Computer Architecture)
2011 - 2013 - Government College of Technology,Coimbatore,India
Bachelor of Engineering (Electrical & Electronics)
2007 - 2011 - Avila Convent Matriculation Higher Secondary School,Coimbatore,India
Skills
- Matlab
- Schematic
- Hardware
- Design
- Government
- Technology
- Cadence Virtuoso
- Computer Architecture
- VLSI
- Verilog
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